It holds the ability to directly access the main memory for read or write operation. DMA controller was designed by Intel, to have the fastest data transfer rate with less processor utilization. We know in order to execute an operation, the microprocessor first fetches the instruction and then decodes it, then further execute it. But individually if the processor is performing all the task inside the system then it unnecessarily keeps the processor busy all the time.
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It holds the ability to directly access the main memory for read or write operation. DMA controller was designed by Intel, to have the fastest data transfer rate with less processor utilization.
We know in order to execute an operation, the microprocessor first fetches the instruction and then decodes it, then further execute it.
But individually if the processor is performing all the task inside the system then it unnecessarily keeps the processor busy all the time. So, to enhance the performance of the processor, an external device is used that can manage data transfer operation between peripherals and memory with least CPU utilization.
Basically, it is nothing but hardware controlled data transfer, where the address and control signals required for transferring the data is generated by an external device. This method of data transfer is known as direct memory access and the external device used for this purpose is known as DMA controller.
Need: We know that generally whenever there exists a need for transfer of data between peripherals and main memory, then first the data is given to the processor by the input device and then the processor further transfers the data to the memory. And at the time of data transfer operation, the processor cannot be able to execute any other operation. Till now we have discussed the need of DMA controller let us move further and understand how DMA executes any instruction for data transfer.
Hence now the processor gets free from any data transfer operation until an interrupt is generated by the DMA controller about the completion of the transfer. The figure below represents a system having a DMA controller: Let us understand the operation of the DMA controller inside the system by considering the idle and active state of the controller.
In the idle cycle of the system, initially when the system gets on, then the processor has control over the system buses, as the switch are connected with the X position. This is so because, in this position, the buses form the connection between main memory and peripherals through the processor. So, in this position, the processor performs the execution of the instruction.
But once, need arises to read the data from the disk. Then the microprocessor sends an instruction to the disk controller about the read operation of that particular data. On fetching the required data, the disk controller peripheral device sends DMA request, i.
This DRQ signal shows that the device directly wants to transfer the data to the memory without disturbing the processor. So, gaining control over the buses, the active cycle of the DMA gets enabled.
Thus now it sends the acknowledge signal DACK to the disk controller that shows that it is now ready for the transfer of data. Now, after acknowledging the disk controller, further, the DMA controller loads the control signal over the bus according to the operation that is to be performed. So, when IOR signal is received by the disk controller then it loads the required data into the data bus.
Thus the disk controller can directly transfer the data to the desired memory location without the CPU utilization. Once the data transfer is accomplished then the DMA controller generates an interrupt by varying switch position from Y to again X.
This indicates the microprocessor about the completion of the data transfer operation. So, by this, the control of the buses is again transferred to the processor and it starts executing the further operation.
This is the basic functioning of the DMA controller inside the system. Let us have a look at the architectural representation of DMA controller. All of the 4 channels can be separately programmed. All the 4 channels hold the bit address and bit counters individually. The permissible data transfer is up to 64 Kb.
The operating frequency ranges between Hz to 3 MHz. The three operations performed are: read transfer, write transfer and verify the transfer. The two operating modes of are master mode and slave mode.
Among all the 4, DRQ0 holds the highest priority, in fixed priority mode. IOR — Pin number 1 — In the master mode of operation, the low signal at this pin indicates the read operation at the peripheral device by the DMA controller. While, in slave mode, it shows that read operation is performed over the internal register by the processor. IOW — Pin number 2 — It is also an active low pin. A low signal at this pin in master mode shows that write operation is performing over the peripheral device.
However, in slave mode, the data bus loads its content at the register. D0 to D7 — Pin number 26 to 30 and 21 to 23 — These are data lines that hold commands and status words in slave mode.
While in the master mode it transfers higher address bytes to the latch. A0 to A3 — Pin number 32 to 35 — These are 4 least significant address lines that act as input and output in slave and master operating mode of the system respectively. A4 to A7 — Pin number 37 to 40 — These are basically lower order address lines produced by the controller in master mode. CLK — Pin number 12 — This pin is used to provide an internal clock frequency signal to CS — Pin number 11 — CS denotes chip select and it is an active low pin.
HRQ — Pin number 10 — The enabling of this pin shows the request to directly access the memory by the peripheral device for read-write operation. MEMR — Pin number 3 — A low signal at this particular pin represents that read operation is performing over the memory by the peripheral device. It gets enabled at the time of memory write operation by the peripheral device. Enabling this pin will demultiplex the address and data bus using latches. VCC — Pin number 31 — The signal for the operation is applied at this pin.
This is all about the operation of the DMA controller along with pin description. You Might Also Like:.
Gagami In the slave mode, they perform as an input, which selects fma of the registers to be read or written. Some of the pins of port C function as handshake lines. These lines can also act as strobe lines for the requesting devices. This signal is used to convert the higher byte of the memory address generated by the DMA controller into the latches. In the Slave mode, command words are carried to and status words from Jobs in Meghalaya Jobs in Shillong.
Direct memory access with DMA controller 8257/8237
It is designed by Intel to transfer data at the fastest rate. Then the microprocessor tri-states all the data bus, address bus, and control bus. Each channel has bit address and bit counter. Each channel can transfer data up to 64kb. Each channel can be programmed independently.
8255 DMA CONTROLLER PDF
Namuro This signal is used to convert the higher byte of the memory address generated by the DMA controller into the latches. When the fixed priority mode is selected, then DRQ 0 has the highest priority and DRQ 3 has the lowest priority among them. Some of pins of port C function as handshake lines. These are the four least significant address lines. This page was last edited on 23 Septemberat These are the active-low and high inactive DMA acknowledge lines, which updates the peripheral requesting device service about the status of their request by the CPU. It is an active-high asynchronous input signal, dmx helps DMA to make ready by inserting wait states. Analogue electronics Interview Questions.