ATTINY13V PDF

By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. All the 32 registers are directly connected to the Arithmetic Logic Unit ALU , allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. PB0 Digital supply voltage. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability.

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Operating Voltage: — 1. Industrial Temperature Range? By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. All the 32 registers are directly connected to the Arithmetic Logic Unit ALU , allowing two independent registers to be accessed in one single instruction executed in one clock cycle.

The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. Digital supply voltage. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability.

As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 12 on page Shorter pulses are not guaranteed to generate a reset.

For compatibility with future devices, reserved bits should be written to zero if accessed. Some of the Status Flags are cleared by writing a logical one to them. Rr Rd? Load Indirect and Pre-Dec. Store Indirect and Pre-Dec. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Also Halide free and fully Green 3.

For Speed vs. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0. E and eA measured with the leads constrained to be perpendicular to datum. Pointed or rounded lead tips are preferred to ease insertion. Dambar protrusions shall not exceed 0. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal.

If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal.

The standard thickness of the plating layer shall measure between 0. D ATtiny13 Rev. Wrong values read after Erase Only operation? Device may lock for further programming? Watchdog Timer Interrupt disabled? Wrong values read after Erase Only operation At supply voltages below 2. In any case, the Write Only operation can be used as intended.

Thus no special considerations are needed as long as the erased location is not read before it is programmed. This will be fixed in revision D. Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effectively turning it into an OTP device.

Selecting longer start-up time will eliminate the problem. A ATtiny13 4. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared.

This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly. This is done by selecting a long enough time-out period. Revision A has not been sampled. The referring revision in this section are referring to the document revision.

Removed Preliminary. Updated Table 12 on page 31, Table 16 on page 39,Table 51 on page Removed Note from Table 15 on page Updated Figure 56 on page Revision not published. C-code examples updated to use legal IAR syntax. Removed rev. Updated Figure 2 on page 3.

Updated Table 12 on page 31, Table 17 on page 40, Table 37 on page 91 and Table 57 on page Updated Figure 54 on page and Figure 57 on page No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.

Atmel does not make any commitment to update the information contained herein. All rights reserved. Other terms and product names may be trademarks of others.

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